M13S128168A sdram equivalent, double data rate sdram.
* Double-data-rate architecture, two data transfers per clock cycle
* Bi-directional data strobe (DQS)
* Differential clock inputs (CLK and CLK )
* DLL a.
Pin Name Function
Pin Name Function
A0~A11, BA0, BA1
Address inputs - Row address A0~A11 - Column address A0~A8
A10/AP: AUTO Precharge BA0, BA1: Bank selects (4 Banks)
DM is an input mask signal for write data. LDM, UDM LDM corresponds to the da.
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